upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

Week 11

Week 12: Timers and other peripherals



Guided activities #12

[P12] Timer1, Timer2 and other peripherals.


Presenting another application. The idea of the P12 project: Enhancing the Johnson counter FSM by means of: (1)  the external CLK source (INT0), or (2) an internal (Timer2). The idea of saving power and PCB space using internal peripherals (timer) instead of external chips (CLK oscillator). 

Timer1 and the external 32.768 kHz crystal CLK. The real-time for a large range of applications.

Other perípherals: A/D, PWM, USART, I2C, etc.


Lecture #12

[P12] Timer1, Timer2 and other peripherals.

Microcontroller applications


Questionnaire #Q3.1 on P9-P10-P11-P12.   


Timer2 and other peripherals.

Description of a final application: 

- Analyse and run this example project #15 in the P_Ch3 project list on a bicycle speed meter (the basics on cyclocomputers).  How to add a new feature like an odometer up to riding distance of 1000 km? Measuring the frequency of a signal.

Final examples on microcontroller applications and research. What kind of project can you attain after this course content?

Other microcontroller or computer platforms such as Arduino or Raspberry Pi. Specialised transducers: sensors and actuators.

Final class on questions & answers on the diffferent projects proposed.



Laboratory #12

[P12] Handling several interrupts TMR0IF and INT0IF

The TMR0 as a time-base for timing applications. A 18.5 s fixed-time timer


1. Specifications. Review the theory on the TMR0 architecture.

In Phase #1 of the design of the timer, the datapath was simply a RAM variable, and the time-base an exernal CLK signal. Let's discuss how the functionality assigned to the counter and the time base circuits in the datapath can be covered by the peripheral TMR0 embedded in the mC .  Replace the previous time-base (external CLK interrupt) by the peripheral TRM0. Study the the fixed-time timer project adaptation. It is organised as an advanced project (datapath & control unit).

- Hardware configuration bits and registers: CLK edge, CLK source, Prescaler selection, TMR0 in 8-bit or 16 bit mode. Hardware interrupt TMR0IF and variable var_TMR0_flag.

- Study the hardware-software diagram of the timer/counter: Prescaler (N1), counter (N2), (software) postscaler (N3)

- How to increase the counting capacity? Software variables like var_Postscaler (N3). 

2. Planning:

2.1 Hardware circuit.

2.2.- Software planning.  State diagram. Variables. CC2 truth table and flow chart. CC1 truth table and flow chart.

3. Development and 4. Test. Let's complete the example amb introduce modifications. 

Run the tutorial timer for 18.5 s. Analyse hardware connections and the important C code sections so that you can write your diagrams and flow charts. Init_system(), read_inputs(), state_logic(), output_logic(), write_outputs() and the interrupt service routine ISR().  Complete in full detail the application block diagram based on a FSM + datapath. Observe the use of the LCD instructions.


- Measure the simulator's "real-time" using break points and step mode.

- Watch the variables of interest.

-  Modify the parameters to generate a TP =  2.23 s.

- Modify the parameters to generate a TP =  5.00 s when the XTAL is 12 MHz.

- Explain why there is TP inaccuracy. How to solve it? Try the TMR2 to replace the TMR0. Which are the main advantages?

- Discusion on the limitations of the TMR0. References.  More topics related to hardware timers: timer overhead, run-time overhead.


This is the due date for the PLA#3.1. (Project PL, June 9


5 min. for answering the UPC questionnaire.


Presentation of circuit prototypes. These are the files.