﻿ Digital Circuits and Systems - Circuits i Sistemes Digitals (CSD) - EETAC - UPC
 Bachelor's Degree in Telecommunications Systems and in Network Engineering

## Week 10: Basic I/O, interrupts and FSM structure

[10/12]

Guided activities #10

 [P9] Examples on polling inputs and writing outputs (digital I/O)

Let's continue with the previous example on the Dual_MUX4 and another project:  implement a 1-digit BCD adder, just another combinational circuit like in P3, but this time using a μC and a program written in C language and compiled, instead of logic gates. The idea is to learn about program organisation and basic I/O using ports at the bit level (logic bitwise operations: AND, OR, shift, NOT, etc.)

- Let's focus or attention in write_outputs().

[15/12]

Lecture #10

 [P10] FSM design programming in C. The 4-bit data transmitter - Detecting events using external interrupts.

Reviewing the projects solved in the lab. Comparing plan X and plan Y examples.

Solving another FSM: The 4-bit data transmitter.

- The interrupt mechanism for detecting events (external inputs falling or ring edges). INT0IF, INT0IE, GIE, etc.

- The concept of the interrupt vector to execute the ISR() special function. The concept of the stack memory.

- Software-hardware diagram. Variables in RAM memory, init_system, read_inputs, write_outputs,

Review other examples of the same kind where the external interrupt mechanism is used in a similar way to detect edges from push-buttons or CLK, for instance:  5-bit Gray counter, chip 74HC4017, 6-bit Johnson counter, etc.

As a complement this class you are invited to read books on basic theory on microcontrollers: library. Find answers to questions.

[14/12]

Laboratory #10

 [P10] FSM in C. State enumeration (Plan X). Large counters (Plan Y) - Interrupts to detect signal events (rising or falling edges)

Detecting signal transitions (rising and falling edges) by means of interrupts to the main program.

The interrupt mechanism. Interrupt hardware flags from peripheral sybsystems (external pins, timers, A/D, USART, etc). Software variables associated to interrupt flags in the ISR() function.

IDE project. Run/stop, step mode, watch window, execution time of a section of code, break points, etc.

Implement a FSM using C language (plan X, enumerationg states): the Counter_BCD_1digit project as a FSM tutorial.

In the general diagram, you see that the main program runs continuously, updating current_state in each loop of the main program. If you have larger C code, it takes longer to refresh the state variable. If you change the crystal quartz oscillator frequency, it will also take a different time to refresh the state variable.

Therefore, how to synchronise operations like state transitions in a FSM each time an active CLK edge is detected as it was done in Chapter 2? --> Using an external CLK (or an internal one from a peripheral such a timer in P12) that will generate an interrupt to the main program.

Another similar project --> Implement a FSM using C language (plan Y, large number of states): the Counter_mod256  or any other large counter such as a Counter_mod6578.

How that large numbers of states are saved?  If there are too many states, the FSM cannot be enumerared, thus, let's organise the architecture as in the chapter 2 plan Y, which consisted in using the current_state as a vector variable. This time a varable type char, int, etc. (depending on the number of bits required).  A char variable can hold up to 256 states. A int variable can hold up to 65236 states.

This is the due date for the PLA#3.1. (Project PK,  delayed June 5)