upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

Week 4

Week 5: Designing large combinational circuits

Week 6



Guided activities #5

[P3-P4] Other arithmetic circuits and Arithmetic and Logic Units (ALU)


Other basic operations in radix-2: comparison, multiplication, bit-shifting. Study the 1-bit comparator complete tutorial example Comp_1bit, in this case a plan A (flat design based on an SoP structural architecture).

Other basic operations in radix-2: multiplication. Play with an 8-bit multiplier (Mult_8bit).

Other arithmetic circuits for 2C integers similar to the ones proposed in your PLA#1.2 (the design of a selectable_add_subt_comp_12bit) to allow further practice about the plan C2:

The general architecture of an arithmetic and logic unit (ALU): performing several operations in parallel and then selecting only one result. Example classic chip: 74LS181.



Laboratory #5

[P4] Radix-2 and 2C numbers and circuits. Measurement of a circuit's operational speed

Circuit propagation delay.

Gate-level simulation for circuit's propagation delay measurement


A final layout of the main topics to be covered of arithmetic circuis and technologies.

The basics of propagatio delays. This is the tutorial on gate-level simulation and the timing analyser tool: Measure the maximun speed of processing for a given target chip of the Int_Add_Subt_8bit in P4. All the necessary files for developing and testing this circuit.

In the lab we have some commercial CPLD and FPGA target chips where to synthesise our circuits. For instance:

Xilinx XC2C256-TQ144 - 7 Spartan-3E XC3S500E-FG320
Intel-Altera MAX II EPM2210F324C3 Cyclone IV EP4CE115F29C7N
Lattice ispMach4128V TQFP100 MachXO


Let's repeat again with another example: use the 10-bit binary adder required in the PLA#1.2 (Adder_10bit) for demonstrating both, how to translate a plan C2 schematic into VHDL, and how to measure the propagation delay of a circuit. Let's use for instance the Adder_8bit plan and VHDL file to copy and adapt them in this session.

Outcomes: These are example files developed in the session: Entity Adder_10bit, Plan C2 for the Adder_10bit, and the VHDL file Adder_10bit.vhd, which has the components Adder_4bit.vhd and Adder_1bit.vhd the tutorials. This is a convenient testbench Adder_10bit_tb.vhd.

And finally, which is the difference between a ripple carry and a carry-look ahead adder?

Other ideas

- Discuss the method of the plan C2 to implement larger circuits using simpler blocks hierarchically:

- Discussion and Q & A on the Selectable _add_subt_comp_10bit for the PLA#1.2.



Lecture #5

[P4]  Planning circuits for maximising processing speed.

[P5] Chapter II: Sequential systems. 1-bit asynchronous memory cell: RS latch


- The introductory ideas on propagation time in logic circuits, technology flat schematic for a target chip and its post-synthesis model in VHDL (the VHO file)

This is the Project D in P3: A 4-bit carry-lookahead adder. The idea of a circuit's processing speed. Comparing internal design strategies: ripple-carry versus carry lookahead. All the necessary files are in this link

 Thus, to summarise this lesson, two kind of experiments are possible:

(1) A circuit synthesised for different PLD's. Different technologies or different vendors imply different speeds of processing.

(2) A circuit planned using different strategies synthesised in a given PLD. For instance, a ripple-carry and a carry lookahead adder will have different speeds of processing. Tutorial on the design of the Adder_4bit using carry-lookahead techniques.

Chapter II: Sequential systems

Let's start the Chapter 2 on sequential circuits discovering the RS latch that works like this.

This device allows writing and reading a bit of data, and thus implements the memory of a digital circuit, which is a fundamental concept.

The first question to rise is: How to build a RS latch from logic gates that you know from Chapter 1?