Week 3: Designing standard (classic) combinational chips 

[08/10] 

Guided activities #3 
[P2] Standard combinational logic circuits: encoders and decoders. [P2] Design flow concept map for combinational circuits. Examples of application of the design flow 

Once we have understood the basic ideas on Boole's algebra and circuit analysis, and the basic standard combinational blocks were presented, let us start designing such circuits. We already have done it for the multiplexers such as the MUX_8. This is the framework: concept map and the VHDL design flow that we'll go repeating once and again for every chip and design plan.
Planning alternative ways for designing circuit architectures in VHDL:
Plan A) Structural (flat)  One VHDL file using equations
Plan B) Behavioural (flat)  One VHDL file using the truth table or algorithm
Plan C1) Structural (hierarchical)  One VHDL using equations (complicated/not recommended)
Plan C2) Structural (hierarchical)  several VHDL files using equations COMPONENTS and SIGNALS. This is the best design approach and so, from P3 and on most of the projects will be organised in this fashion.
Let's do the same for decoders, encoders, demultiplexers, Gray to binary converters, hexadecimal to 7segment decoders, etc. So, for each chip, will be able to choose between plan A, B, or C2.

[13/10] 

Lecture #3 
[P2] Examples of incomplete logic functions [P3] Plan C2. Designing logic functions using the method of decoders (MoD) or the method of multiplexers (MoM). 

Let's continue designing standard logic circuits.
Decoders. (1) Symbol, (2) truth table or equations, (3) timing diagram, (4) commercial chip, (5) internal design (Plan A, B, C1 or C2), (6) how to expand them (Plan C2)?
 Plan A. Discussion of the Dec_3_8 decoder using equations.
 Plan B. Discussion of the Dec_3_8 decoder using the truth table, algorithm or any other highlevel interpretation.
And the same for encoders (and also later for arithmetic circuits).

Yet another example, the Hex_7seg_decoder. It is a circuit to drive the typical 7segment displays. Run the circuit in Proteus to figure out how it works.
 Plan A. HEX to 7 SEG decoder (type 74LS47). Using a structural approach based on minimised equations (SoP / PoS).
 Plan B. HEX to 7 SEG decoder (type 74LS47). Using a behavioural (highlevel) description (truth table or algorithm) approach.
Let's discuss further about electrical chareacteristics of logic gates:
 How to drive a 7segment commonanode or commoncathode display?
 How to calculate the limiting resistor? You can run this Circuit in Proteus to get an idea on voltage levels, currents, power consumption and logic values. Read more about electrical characteristics. (VOHmin, VOLmax, noise margins, etc.)
An finally, an example of incomplete function where the truth table is not completelly specified. Let's discuss the example of the tank water level meter.

[14/10] 

[P2] Comparing implementations: flat (single VHDL file) design (structural/behavioural/hierarchical) Circuit MUX8  plan A: structural, plan B: behavioural 

Tutorial on the design of the circuit MUX_8 (type 74HCT151) proposed in P2 where is completely explained:
Following the plan A) Flat structural VHDL. Using Minilog (tbl file) to get the SoP equation and then write it in VHDL. These are the files of interest to start.: the circuit mux_8.vhd and a testbench mux_8_tb.vhd from which you can copy the constant Min_Pulse and the stimulus process

Following the plan B). Flat behavioural VHDL. Copy and adapt source files and run the complete project. This time, you have up to 3 different files because we have infered 3 highlevel interpretations for the truth table. This is the circuit MUX_8.vhd. using the flow chart version (3) to be placed at:
L:\CSD\P2\MUX_8B3\MUX_8.vhd
You can use the same testbench mux_8_tb.vhd again, it doesn't matter that you have another idea for the architecture, the testbench can be the same because the entity does not change.
This is a tutorial on a similar circuit: a dual 4channel multiplexer (Dual_MUX4) in case you need to find ideas on how to copy and adapt VHDL files.
It is time for printing and reading the preparatory laboratory assignment PLA#1.1 for the next Lab #4 which is about designing combinational circuits using alternative plans A or B. In class time, we'll assign you individually a plan A or a plan B to solve the project.
Extra material to analyse in class or in your own study time:
1) Following the plan C1). Flat hierarchical VHDL. Find the schematic and the MUX_8.vhd file in our P2 page and run the complete project. [NOTE: This plan C1 is not recommended > because it is far better the plan C2 which uses several VHDL files to represent a hierarchical structure].
ADDITIONAL TASK: Compare RTL views of the 4 or 5 projects (Plan A, B1, B2, B3, C1) and discuss them. What about technology schematic views, which is the real circuit MUX_8 synthesised in the target chip?
Additional concepts and tutorials to study and practise
As an EETAC  UPC student, you can borrow books or download their electronic versions on the subject. We hugely recommend reading books on the subject to complement your class notes and get a broader view of the whole area of digital electronics.

Hint: study and solve projects to the end. Print & write the corresponding 4sheetofpaper report for each project adding theory and whatever else you find useful in order to have good materials and class notes to study the subject. Simulate testbenches to certify that your design is correct. Annotate your questions and find answers in office time or at next classes. Remember that we are assuming that up to now: 3 weeks of classes > 15 hours of tuition in class and 15 hours out of class of your study time.