upc eetac_1 Bachelor's Degree in Telecommunications Systems and in Network Engineering

Planning

Week 1: Analysis of simple combinational circuits. Boole's Algebra

Week 2



[24/09]

Guided activities #1

[P1] Course presentation and basic logic gates

AND, OR, NOT, XOR, NOR, NAND, NXOR

 

This is the course presentation.

The concept of a logic gate represented in two complementary ways (schematic/symbol/logic diagram and logic equation) and its truth table to describe its specifications or how does it works. Class notes (1)

Welcome message


[29/09]

Lecture #1

[P1] Circuit analysis, gates and CSD project design flow

Circuit analysis using Boole's Algebra (method #3)

How to organise a project in CSD? 

Logic gates and technology (voltage levels)

 

P1: Section A - method III: Plan, develop and test - Boole's algebra and equations

As we did in the lab, let's start with the analysis of a section of the Circuit_C proposed in P1 to be named Circuit_W.

Let's discuss the general plan that will include up to 4 different proceedings to analyse the circuit.  So, the pen-and-paper analysis, method #3 of the Circuit_W gives you firstly the PoS (equation 1) and then the truth table by means of the expression of the product of maxterms. Class notes: (1), (2) and other ideas on maxterns and minterns (3)

Alternatively, if you develop further the circuits' equation you'll get a SoP which becomes the sum of minterns once you've added the missing variables in each product using x = x(y+y') = x·y + x·y'

 

Do it again for the Circuit_C , Circuit K  or aother similar gate-based circuits. The more you practise the better. Other examples are here.

 


How to organise each project or problem in CSD? Each project section must be in a different sheet of paper (4 sheets of paper at least).

1. Specifications

What do I have to do? Theory and other tutorials.

2. Planning

Graphics, schematics, circuits, models, concept maps, general ideas, process flowchart, bullet lists, etc.

3. Development

Commented computer source files, computer results, graphics, pictures, timing diagrams, truth tables, etc. whatever necessary to demonstrate that you solved the problem following your plan.

4. Test

Verifications, comparisons, simulator and computer results, explanations and discussions to demonstrate that your project works as expected.

This example (1) shows how to write a report of a circuit analysis using the method I based on Proteus simulations. This example (2) shows how the design can be organised  and reported following the 4-section template. Furthermore, because most of the analysis and designs will require computer tools and applications, you must create a folder for storing the files from each project in our virtual desktop and SMB drive. Print and comment the most meaningfull files and graphics.

 

Further discussion on logic voltages (VoH, VoL, ViH, ViL, Vcc, GND), technology 74LS (for instance the chip 74LS04) or the CMOS 4069. Noise Margin High (NMH) and Noise Margin Low (NML), output current, etc.

This is another version of the Circuit_W where you can add to the digital electronic circuit Chip1 some buttons, switches, LED's and even relays and motors. Play with the circuit and pay attention to the real voltages that represent '0' and '1' signals.


[28/09]

Laboratory #1

[P1]  Circuit analysis: determine the truth table using methods I and II

Method I: Circuit schematics. Electronic circuits simulation using Proteus

Method II: Circuit equation. WolframAlpha numerical engine  

 

P1: Section A - method I: Plan, develop and test: Proteus simulation and virtual lab.

In the lab, accordingly to our plan, we'll run the method I for obtaining the Circuit_W truth table W = f (D1, D0, A, B): a Proteus simulation. Be aware to place the project file here (virtual desktop, SMB drive):  

L:\CSD\P1\Proteus\Circuit_W\Circuit_W.pdsprj

Some lab notes (1), tutorial and a video rec. on how to proceed with Proteus to deduce the truth table. For instance, Circuit_W.pdsprj is the circuit copied and adapted from the Proteus tutorial.

Message 2 on the SMB disk and the Windows 10 VD.


P1: Section A - method II: Plan, develop and test - WolframAlpha numerical engine.

This is another way to deduce a circuits' truth table, let's use a web-based calculator (or computer engine) like WolframAlpha. This is a text file containing some equations from the Circuit _W to copy and paste into WolframAlpha. Lab notes (1), tutorial and video rec. on how to proceed with WolframAlpha. Remember that is important to reorder, if necessary, the columns of the truth table W = f (D1, D0, A, B). 

Evidently, in the end, the two methods experimented (and the other two refered in the plan to be solved the next sessions) will produce the same truth table. Thus, you can assess the project yourself and start writing the report.

 


Additional concepts and tutorials to study and practise

Workload in one week of study time: five hours in class and five out of class.

Projects solved: Circuit_W in three methods (at least twelve pages). In this case, the specifications are the same all the time, so photocopy the specifications sheet so that you can archive each project in its own folder.

1. Specifications 2. Planning 3. Development 4. Test
Circuit_W truth table Method I Proteus tool Using the solution from other project
Circuit_W truth table Method II WolframAlpha tool Using the solution from other project
Circuit_W truth table Method III handwritten analysis Using the solution from other project

folders

 

This is the list of proposed projects in this P1. So, be professional, do the work in a weekly basis and do not hesitate to ask us in class or by email as many questions as necessary to advance proficiently.