-- VHDL Test Bench Created from source file matrix_encoder_16key.vhd -- 04/13/17 11:59:57 -- -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_vector for the ports of the unit under test. -- Lattice recommends that these types always be used for the top-level -- I/O of a design in order to guarantee that the testbench will bind -- correctly to the timing (post-route) simulation model. -- 2) To use this template as your testbench, change the filename to any -- name of your choice with the extension .vhd, and use the "source->import" -- menu in the ispLEVER Project Navigator to import the testbench. -- Then edit the user defined section below, adding code to generate the -- stimulus for your design. -- LIBRARY ieee; LIBRARY generics; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE generics.components.ALL; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS COMPONENT matrix_encoder_16key PORT( CLK : IN std_logic; CD : IN std_logic; Columns : IN std_logic_vector(3 downto 0); Data : OUT std_logic_vector(3 downto 0); GS : OUT std_logic; Rows : OUT std_logic_vector(3 downto 0) ); END COMPONENT; SIGNAL CLK : std_logic; SIGNAL CD : std_logic; SIGNAL Columns : std_logic_vector(3 downto 0); SIGNAL Data : std_logic_vector(3 downto 0); SIGNAL GS : std_logic; SIGNAL Rows : std_logic_vector(3 downto 0); -- Clock period definitions constant CLK_period : time := 5 ms; --(FCLK = 200 Hz) BEGIN uut: matrix_encoder_16key PORT MAP( CLK => CLK, CD => CD, Columns => Columns, Data => Data, GS => GS, Rows => Rows ); -- *** Test Bench - User Defined Section *** -- Clock process definitions CLK_signal :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin -- A kind of power supply turn on wait for 100 ns; wait for CLK_period*2.3; CD <= '0'; Columns <= "1111"; wait for CLK_period*2.56; -- Clear direct CD <= '1'; wait for CLK_period*4.56; CD <= '0'; wait for CLK_period*8.75; -------------------------------------------------------------------------------- Columns <= "1011"; -- this means that some key has been pressed -- Let's see which one is it wait for CLK_period*6.46; Columns <= "1111"; -- this means that the key is released wait for CLK_period*1.5; Columns <= "1011"; -- this means that some key has been pressed -- Let's see which one is it wait for CLK_period*3.46; Columns <= "1111"; -- this means that the key is released wait for CLK_period*3.8; Columns <= "1011"; -- this means that some key has been pressed -- Let's see which one is it wait for CLK_period*2.46; Columns <= "1111"; -- this means that the key is released wait for CLK_period*1.2; Columns <= "1011"; -- this means that some key has been pressed -- Let's see which one is it wait for CLK_period*3.46; Columns <= "1111"; -- this means that the key is released wait for CLK_period*2; wait; -- end of user generated stimulus end process; -- *** End Test Bench - User Defined Section *** END;